Warrick Lo

Two-Stage CMOS Operational Amplifer Design with the SKY130 PDK

Analog Design SKY130 Draft
Schematic of the operational amplifier circuit.
Figure 1. Schematic of the operational amplifier circuit.

An operational amplifier designed for the SkyWater 130 nm process.

Git: https://git.warricklo.net/opamp (mirror)
Canonical URL: https://warricklo.net/opamp

Contents

  1. Overview
    1. Performance results
  2. Design Process
    1. Design constraints
  3. Simulation Results
    1. Open-loop response
    2. Closed-loop response
  4. Project Report

Overview

Parameter Specification Achieved
Output common-mode voltage 0.9 V 0.898 V
Power consumption ≤ 400 μW 282.2 μW
Differential output swing ≥ 1.2 V ?
Low-frequency differential gain ≥ 46 dB 50.48 dB
Small-signal unity gain frequency ≥ 60 MHz 66.2 MHz
Phase margin ≥ 60° & ≤ 90° 75.2°
Slew rate ≥ 20 V/μs 75.8 V/μs
Table 1. Performance results of the final design.

Design Process

Screen capture of the open-loop testbench
Figure 2. Screen capture of the open-loop testbench. Using ngspice's MEAS command, we found the open-loop gain to be 50.47520 dB.
Parameter Constraint
Supply voltage 1.8 V
Reference voltage 0 V
Input common-mode voltage 0.9 V
Maximum length of transistor 650 nm
Maximum width per multiplier 4 μm
Maximum fingers per multiplier 1
Maximum number of multipliers 50
Table 2. Design constraints.

Simulation Results

Open-loop Bode plot
Figure 3. Frequency response of the op-amp in the open-loop configuration.
Closed-loop Bode plot
Figure 4. Frequency response of the op-amp in the closed-loop configuration.

Project Report

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This page is a draft.