Simple RISC Machine

Computer Architecture FPGA ASIC Design

In CPEN 211 at UBC, we architect a RISC processor in SystemVerilog using the DE1-SoC as part of the labs. For additional bonus grades, you can make the processor fully Turing complete and enter a competition with the rest of the class to build the most efficient processor. I teamed up with Krish Thakur and in the end, our processor ended up in third place.